1T1R resistive random access memory, and manufacturing method thereof, transistor and device

ABSTRACT

The present disclosure provides a 1T1R resistive random access memory and a manufacturing method thereof, and a device. The 1T1R resistive random access memory includes: a memory cell array composed of multiple 1T1R resistive random access memory cells, each 1T1R resistive random access memory cell including a transistor and a resistance switching device (30). The transistor includes a channel layer (201), a gate layer (204) insulated from the channel layer (201), and a drain layer (203) and a source layer (202) disposed on the channel layer (201), and the drain layer (203) and the source layer (202) are vertically distributed on the channel layer (201). The resistance change device (30) is disposed near the drain layer (203). The disclosure reduces the area of a transistor, thereby significantly improving the memory density of the resistive random access memory.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation of International Application No.PCT/CN2019/077477, filed on Mar. 8, 2019, the disclosure of which ishereby incorporated by reference in its entirety.

TECHNICAL FIELD

The disclosure relates to the field of memory technology, and inparticular, to a 1T1R resistive random access memory and a manufacturingmethod thereof, a transistor, and a device.

BACKGROUND

Resistive random access memory (RRAM) is a new type of non-volatilememory (NVM) that implements data storage based on the variableresistance of a device, which has attracted much attention due to itsadvantages such as low operating power consumption and fast read/writespeeds. 1T1R is a common memory cell structure of RRAM, where T standsfor transistor, and R stands for resistance switching device.

A current RRAM array architecture and a memory cell with an 1T1Rstructure are shown in FIG. 1 a and FIG. 1 b , where FIG. 1 a is aschematic diagram of the RRAM array architecture with the 1T1R structurein the prior art, and FIG. 1 b is a schematic diagram of a single 1T1Rmemory cell in the prior art. As shown in FIG. 1 b , each memory cellcomprises a transistor 10 and a resistance switching device 11. Thetransistor 10 is composed of a monocrystalline silicon substrate 100, asource 102, a drain 104, a gate 101, and a gate dielectric layer 103.The resistance switching device 11 is composed of a lower electrode 110,a resistance switching layer 111, and an upper electrode 112. The drain104 of the transistor 10 is electrically connected to the lowerelectrode 110 of the resistance switching device 11 through a contact106, a metal layer 107, a via 108, and the like. The upper electrode 112of the resistance switching device 11 is electrically connected to themetal layer 109 through a via 108. The metal layer 109 is connected to abit line (BL for short). The resistance of the resistance switchingdevice changes with a voltage applied, and according to a value of theresistance, it can be divided into a low resistance state and a highresistance state which may corresponding to logic “1” and “0”,respectively. The process of writing the low resistance state is called“set”, specific steps of which are as follows: turn on a transistorthrough a word line (WL for short) voltage to select a correspondingrow; apply a write voltage to a BL of a corresponding column, and asource line (SL for short) of the corresponding column is grounded, andthe voltage on BL can complete the “set” process of RRAM. The process ofwriting the high resistance state is called “reset”, and its steps aresimilar to writing the low resistance state, except that the writevoltage is applied to the SL of the corresponding column, and the BL isgrounded. Steps of a reading process are as follows: a WL selects acorresponding row, a SL of a corresponding column is grounded and areading voltage is applied to a BL to complete the reading process.During the reading process, the transistor is used to gate theresistance switching device, thereby avoiding the problem of misreading.

However, an area of the foregoing 1T1R memory cell mainly depends on anarea of the transistor, and the area of the transistor in the foregoingstructure is difficult to be reduced, and thus the area of the memorycell can hardly be made small, thereby limiting the memory density.

SUMMARY

The disclosure provides a 1T1R resistive random access memory, and amanufacturing method thereof, a transistor and a device, which reducethe area of the transistor, thereby significantly improving the memorydensity of the resistive random access memory, and solving the problemof the existing 1T1R resistive random access memory that the memorydensity is limited due to that the transistor area cannot be reduced.

This disclosure provides a 1T1R resistive random access memory,including: a memory cell array composed of multiple 1T1R resistiverandom access memory cells, each 1T1R resistive random access memorycell including a transistor and a resistance switching device;

the transistor includes a channel layer, a gate layer insulated from thechannel layer, and a drain layer and a source layer disposed on thechannel layer, where the drain layer and the source layer are verticallydistributed on the channel layer;

the resistance switching device is disposed near the drain layer, andtwo ends of the resistance switching device are used to connect to thedrain layer and a bit line, respectively, and the gate layer is used toelectrically connect to a word line, and the source layer is used toconnect to a source line.

In a specific implementation of this disclosure, specifically, the drainlayer is disposed on one end of a top end and a bottom end of thechannel layer, and the source layer is disposed on the other.

In a specific implementation of this disclosure, specifically, the gatelayer is disposed around an outer wall of the channel layer, and a gatedielectric layer is disposed between the gate layer and the channellayer.

In a specific implementation of this disclosure, specifically, furtherinclude:

an isolation layer, where the isolation layer is disposed around anouter surface of the gate layer, and is used to isolate adjacenttransistors.

In a specific implementation of this disclosure, specifically, furtherinclude: a mask layer, where the mask layer covers at least the sourcelayer or covers at least the drain layer.

In a specific implementation of this disclosure, specifically, furtherinclude: a buried oxide layer, and one of the buried oxide layer and themask layer covers at least the source layer, and the other covers atleast the drain layer.

In a specific implementation of this disclosure, specifically, furtherinclude: a first dielectric layer, where the first dielectric layer isprovided on one end surface of the transistor, and at least a firstmetal wire is provided in the first dielectric layer, where the firstmetal wire is used to electrically connect one of the source layer andthe drain layer near the first dielectric layer to a corresponding wire.

In a specific implementation of this disclosure, specifically, furtherinclude: a second dielectric layer, where the second dielectric layer isdisposed on one end surface of the transistor facing away from the firstdielectric layer, and at least a second metal wire is provided in thesecond dielectric layer, where the second metal wire is used toelectrically connect one of the source layer and the drain layer nearthe second dielectric layer to a corresponding wire.

In a specific implementation of this disclosure, specifically, a thirdmetal wire is further disposed in the first dielectric layer or thesecond dielectric layer, where the third metal wire is used to connectthe gate layer to a corresponding word line electrically.

In a specific implementation of this disclosure, specifically, furtherinclude: a slide wafer, where the slide wafer is provided on one of thefirst dielectric layer and the second dielectric layer far from theburied oxide layer.

In a specific implementation of this disclosure, specifically, theresistance switching device includes a lower electrode, a resistiveswitching layer and an upper electrode which are sequentially stacked,where the lower electrode is electrically connected to the drain layer,and the upper electrode is electrically connected to the bit line.

In a specific implementation of this disclosure, specifically, the firstmetal wire, the second metal wire, and the third metal wire eachcomprise at least one contact and at least one metal layer, the gatelayer, the source layer and the drain layer are respectivelyelectrically connected to corresponding metal layers through thecontact, the metal layer in the first dielectric layer is electricallyconnected to first pads exposed on the first dielectric layer, and themetal layer in the second dielectric layer is electrically connected toa second pads exposed on the second dielectric layer.

In a specific implementation of this disclosure, specifically, thechannel layer is a columnar structure, and the gate layer is an annularstructure disposed around a sidewall of the columnar structure.

In a specific implementation of this disclosure, specifically, the masklayer, the buried oxide layer, the isolation layer, and the gatedielectric layer are all made of silicon oxide.

The disclosure also provides a transistor, including a channel layer, agate layer insulated from the channel layer, and a drain layer and asource layer that are disposed on the channel layer, where the drainlayer and the source layer are vertically distributed on the channellayer.

In a specific implementation of this disclosure, specifically, the drainlayer is disposed on one of a top end and a bottom end of the channellayer, and the source layer is disposed on the other end.

In a specific implementation of this disclosure, specifically, the gatelayer is disposed around an outer wall of the channel layer, and a gatedielectric layer is provided between the gate layer and the channellayer.

In a specific implementation of this disclosure, specifically, furtherinclude:

an isolation layer, where the isolation layer is disposed around anouter surface of the gate layer, and is used to isolate adjacenttransistors.

In a specific implementation of this disclosure, specifically, furtherinclude: a mask layer, where the mask layer covers at least the sourcelayer or covers at least the drain layer.

In a specific implementation of this disclosure, specifically, furtherinclude: a buried oxide layer, where one of the buried oxide layer andthe mask layer covers at least the source layer, and the other covers atleast the drain layer.

The disclosure further provides a device including the 1T1R resistiverandom access memory as described above.

The disclosure further provides a device including the transistor asdescribed above.

The disclosure provides a manufacturing method for a 1T1R resistiverandom access memory, the method includes:

providing a substrate, where the substrate includes a support layer, aburied oxide layer and a silicon layer which are sequentially stacked;

forming a mask layer on the silicon layer;

forming a single or multiple spaced annular grooves which are extendingfrom the mask layer to the buried oxide layer, so that a single ormultiple columnar structures are formed on the substrate, and a groovebottom of the annular groove extends into the buried oxide layer;

forming a thermal oxide layer on a sidewall of the annular groove;

forming a gate layer by filling polysilicon in the annular groove;

forming a source layer by implanting a P-type doped element or an N-typedoped element into an end of the columnar structure facing the masklayer;

forming a drain layer by implanting a P-type doped element or an N-typedoped element into an end of the columnar structure where the siliconlayer is in contact with the buried oxide layer;

disposing a resistance switching device near the drain layer, where oneend of the resistance switching device is electrically connected to thedrain layer.

In a specific implementation of this disclosure, specifically, beforeimplanting a P-type doped element or an N-type doped element into an endof the columnar structure facing the mask layer, the method furtherincludes:

reducing a thickness of the masking layer to 8 nm to 20 nm.

In a specific implementation of this disclosure, specifically, theforming a thermal oxide layer on a sidewall of the annular groove,includes:

forming a first thermal oxide layer on an inner circular sidewall of theannular groove, where the first thermal oxide layer is used to insulatethe gate layer from the gate dielectric layer of the columnar structure;

forming a second thermal oxidation layer on an outer circular sidewallof the annular groove, where the second thermal oxidation layer is usedto isolate two adjacent gate layers.

In a specific implementation of this disclosure, specifically, beforeimplanting a P-type doped element or an N-type doped element into an endof the columnar structure where the silicon layer is in contact with theburied oxide layer, the method further includes:

removing the support layer;

reducing a thickness of the buried oxide layer to 8 nm to 20 nm.

In a specific implementation of this disclosure, specifically, afterimplanting a P-type doped element or an N-type doped element into an endof the columnar structure facing the mask layer, the method furtherincludes:

forming a lower dielectric layer on the mask layer and on an end surfaceof the gate layer near the mask layer;

forming a gate metal layer, a source metal layer, and first pads that iselectrically connected to the gate metal layer and the source metallayer on the lower dielectric layer;

covering a first inter-metal dielectric layer on the lower dielectriclayer on which the gate metal layer, the source metal layer and thefirst pads are formed, where the gate metal layer and the source metallayer are electrically connected to the gate layer and the source layerthrough a contact, respectively;

disposing a slide wafer on the first inter-metal dielectric layer.

In a specific implementation of this disclosure, specifically, afterimplanting a P-type doped element or an N-type doped element into an endof the columnar structure where the silicon layer is in contact with theburied oxide layer, the method further includes:

forming an upper dielectric layer on the buried oxide layer and on anend surface of the gate layer near the buried oxide layer;

the disposing a resistance switching device near the drain layerincludes:

disposing the resistance switching device on the upper dielectric layerat a position corresponding to the drain layer, where the resistanceswitching device includes a lower electrode, a resistance switchinglayer and an upper electrode that are stacked, and the lower electrodeis electrically connected to the drain layer via a contact.

In a specific implementation of this disclosure, specifically, afterdisposing the resistance switching device on the upper dielectric layerat a position corresponding to the drain layer, the method furtherincludes:

disposing a second inter-metal dielectric layer on the upper dielectriclayer on which the resistive random device is formed;

forming a drain metal layer and a second pads that is electricallyconnected to the drain metal layer on the second inter-metal dielectriclayer, where the drain metal layer is electrically connected to theupper electrode through a contact;

covering a third inter-metal dielectric layer on the second inter-metaldielectric layer on which the drain metal layer and the second pads areformed.

In a specific implementation of this disclosure, specifically, aftercovering a third inter-metal dielectric layer on the second inter-metaldielectric layer on which the drain metal layer and the second pads areformed, the method further comprises:

opening a first opening and a second opening on the third inter-metaldielectric layer at positions corresponding to the first pads and thesecond pads, respectively, where the first opening extends to a surfaceof the first pads, and the second opening extends to a surface of thesecond pads.

In the 1T1R resistive random access memory provided by the disclosure,the transistor includes a columnar channel layer, an annular gate layersurrounding a side surface of the channel layer, and a gate dielectriclayer between the channel layer and the gate layer.

The drain layer is disposed on one of the top surface and the bottomsurface of the channel layer, and the source layer is disposed on theother. The resistance switching device is disposed near the drain layer,and two ends of the resistance switching device are respectively used toconnect to the drain layer and a bit line. The gate layer is used toelectrical connect to a word line, and the source layer is used toconnect to a source line. In the way, the minimum footprint of thetransistor is reduced to 4F², which compared with the transistor in theprior art, is greatly reduced, and thus the area of each 1T1R resistiverandom access memory cell is reduced, and the memory density isincreased. Therefore, the 1T1R resistive random access memory providedin the embodiments reduces the footprint of the transistor and increasesthe memory density, thereby solving the problem of the existing 1T1Rresistive random access memory that the memory density is limited due tothat the transistor area cannot be reduced.

BRIEF DESCRIPTION OF DRAWINGS

In order to explain the technical solutions in the embodiments of thepresent disclosure or the prior art more clearly, the drawings used inthe description of the embodiments or the prior art will be brieflyintroduced below. Obviously, the drawings in the following descriptionare some embodiments of the present disclosure. For those skilled in theart, other drawings can be obtained based on these drawings without anycreative effort.

FIG. 1 a is a schematic diagram of an RRAM array architecture with a1T1R structure according to the prior art;

FIG. 1 b is a schematic diagram of a single 1T1R memory cell accordingto the prior art;

FIG. 1 c is a structural schematic diagram of the top view of atransistor in a 1T1R memory cell in the prior art;

FIG. 1 d is a structural schematic diagram of the cross-sectional viewin the direction A-A in FIG. 1 c;

FIG. 2 a is a structural schematic diagram of the cross-sectional viewof a 1T1R resistive random access memory according to a first embodimentof the present disclosure;

FIG. 2 b is a structural schematic diagram of the top view of atransistor in the 1T1R resistive random access memory according to thefirst embodiment of the present disclosure;

FIG. 2 c is a structural schematic diagram of the cross-sectional viewin the direction B-B in FIG. 2 b;

FIG. 3 is a schematic flowchart of a manufacturing method for a 1T1Rresistive random access memory according to a fifth embodiment of thepresent disclosure;

FIGS. 4 a-4 j are structural schematic diagrams obtained by steps of themanufacturing method for a 1T1R resistive random access memory accordingto the fifth embodiment of the present disclosure.

LIST OF REFERENCE SIGNS

201 channel layer;

202 source layer;

203 drain layer;

204 gate layer;

205 gate dielectric layer;

206 isolation layer;

207 mask layer;

208 buried oxide layer;

30 resistance switching device;

31 upper electrode;

32 resistance switching layer;

33 lower electrode;

41 first dielectric layer;

42 second dielectric layer;

411 lower dielectric layer;

421 upper dielectric layer;

412 first inter-metal dielectric layer;

422 second inter-metal dielectric layer;

423 third inter-metal dielectric layer;

401 first metal wire;

402 second metal wire;

403 third metal wire;

501 first pads;

5011 first opening;

502 second pads;

5021 second opening;

51 first metal layer;

52 second metal layer;

53 third metal layer;

54 fourth metal layer;

61 first contact;

62 second contact;

63 third contact;

64 fourth contact;

70 slide wafer.

DESCRIPTION OF EMBODIMENTS

In order to make the objectives, technical solutions, and advantages ofthe embodiments of the present disclosure clearer, the technicalsolutions in the embodiments of the present disclosure will be clearlyand completely described with reference to the accompanying drawings inthe embodiments of the present disclosure. Obviously, the describedembodiments are part of the embodiments of the present disclosure, butnot all the embodiments. Based on the embodiments in the presentdisclosure, all other embodiments obtained by those skilled in the artwithout creative efforts shall fall within the protection scope of thepresent disclosure.

As described in the background, in the prior art, the 1T1R resistiverandom access memory has a problem of limited memory density. Afterresearch by the inventors, it is found that the reason for this problemis as follows. The area of the memory cell in the existing 1T1Rresistive random access memory mainly depends on the area of thetransistor 10, the structure of which is shown in FIG. 1 b to FIG. 1 d ,where the source layer 102 and the drain layer 104 are located on theleft and right sides of the gate layer 101, respectively. Duringoperation, the transmission of carriers is along the horizontaldirection, which eventually makes the footprint of the transistorapproximately 10F², where F is the characteristic line width of theprocess node. Such a structure of the transistor makes it impossible toreduce the footprint of the transistor, thereby causing the area of thememory cell to be hardly made small, thereby limiting the memorydensity.

Based on the above reasons, the present disclosure provides a 1T1Rresistive random access memory. The 1T1R resistive random access memoryprovided in the present disclosure will be described below withreference to several embodiments.

First Embodiment

FIG. 2 a is a structural schematic diagram of the cross-sectional viewof a 1T1R resistive random access memory according to the firstembodiment of the present disclosure. FIG. 2 b is a structural schematicdiagram of the top view of a transistor in the 1T1R resistive randomaccess memory according to the first embodiment of the presentdisclosure. FIG. 2 c is a structural schematic diagram of thecross-sectional view in the direction B-B in FIG. 2 b.

As shown in FIGS. 2 a-2 c , the 1T1R resistive random access memoryincludes: a memory cell array composed of multiple 1T1R resistive randomaccess memory cells, where FIG. 1 a can be specifically referred to forthe memory cell array composed of multiple 1T1R resistive random accessmemory cells, where each 1T1R resistive random access memory cellincludes a transistor and a resistance switching device 30. In thisembodiment, in order to reduce the footprint of the transistor,specifically, the transistor includes a channel layer 201, a gate layer204 insulated from the channel layer 201, and a drain layer 203 and asource layer 202 disposed on the channel layer 201, and the drain layer203 and the source layer 202 are vertically distributed on the channellayer 201, that is, the drain layer 203 and the source layer 202 aresequentially distributed along the vertical direction of the channellayer 201, e.g. the drain layer 203 may be located above the channellayer 201, the source layer 202 is located below the channel layer 201,and the drain layer 203 and the source layer 202 are vertically arrangedon the channel layer 201. In this disclosure, since the drain layer 203and the source layer 202 are vertically distributed on the channel layer201, compared with the horizontal distribution of the drain layer andthe source layer in the prior art (as shown in FIG. 1 b ), the footprintof the transistor in the horizontal direction is greatly reduced in theprovided embodiment.

It can be obtained by measuring the transistor provided in thisembodiment that the transistor has a minimum footprint of 4F² only, andthe footprint of the transistor provided in this embodiment is greatlyreduced compared with the footprint 10F² of the transistor in the priorart, which leads to a great reduction in the area of a single 1T1Rresistive random access memory cell and thereby significant improvementof the memory density.

In this embodiment, the resistance switching device 30 needs to beelectrically connected to the drain layer 203. Therefore, the resistanceswitching device 30 is disposed near the drain layer 203, and two endsof the resistance switching device 30 are respectively used to connectto the drain layer 203 and a bit line. In this embodiment, the gatelayer 204 is used to electrically connect to a word line, and the sourcelayer 202 is used to connect to a source line.

In this embodiment, the channel layer 201 is specifically a siliconlayer, and the element doped in the channel layer 201 is different fordifferent types of transistors (N-type transistors and P-typetransistors). For example when the transistor is an N-type transistor,the channel layer 201 is often doped with boron (P-type doping), andwhen the transistor is a P-type transistor, the channel layer 201 isoften doped with phosphorus (N-type doping), with a possible dopingconcentration of 1E15 cm⁻³.

In this embodiment, the gate layer 204 is specifically made of dopedpolysilicon; the source layer 202 and the drain layer 203 are formed bya heavily doped silicon layer made of a silicon layer doped with anN-type doped element or a P-type doped element. The gate dielectriclayer 205 is used to insulate the gate layer 204 from the channel layer201 and is specifically made of silicon oxide. In this embodiment, thethickness of the gate dielectric layer 205 may be 10 nm. In thisembodiment, the gate layer 204, the source layer 202, the drain layer203 and the gate dielectric layer 205 include but not limited to theforegoing materials, and can also be made of other materials.

Therefore, in the 1T1R resistive random access memory provided in thisembodiment, the transistor includes a channel layer 201, a gate layer204 insulated from the channel layer 201, and a drain layer 203 and asource layer 202 that are disposed on the channel layer 201, and thedrain layer and the source layer are vertically distributed on thechannel layer. In this way, the minimum footprint of the transistor isreduced to 4F². which compared with the transistor in the prior art, isgreatly reduced, and thus leads to a great reduction in the area of each1T1R resistive random access memory cell, and an increase in the memorydensity. Therefore, the 1T1R resistive random access memory provided inthis embodiment reduces the footprint of the transistor and increasesthe memory density, thereby solving the problem of the existing 1T1Rresistive random access memory that the memory density is limited due tothat the transistor area cannot be reduced.

Further, on the basis of the foregoing embodiment, in this embodiment,the drain layer 203 is disposed on one of the top end and the bottom endof the channel layer 201, and the source layer 202 is disposed on theother. Specifically, as shown in FIG. 2 c , the channel layer 201 has aside surface, a top surface, and a bottom surface. The gate layer 204 isdisposed around the side surface of the channel layer 201 in a round,and finally the gate layer 204 and the channel layer 201 form a columnarstructure together. Meanwhile, the drain layer 203 is disposed on thetop surface of the channel layer 201 and the source layer 202 isdisposed on the bottom surface, that is, the drain layer 203 and thesource layer 202 are located on the upper and lower ends of the channellayer 201, respectively. In this embodiment, for example, the drainlayer 203 may be disposed on the top surface of the channel layer 201and the source layer 202 may be disposed on the bottom surface of thechannel layer 201, or the source layer 202 may also be disposed on thetop surface of the channel layer 201 and the drain layer 203 may bedisposed on the bottom surface of the channel layer 201, to form avertical columnar transistor, during the operation of which, carriersmigrate in a vertical direction.

In the embodiment, the gate layer 204 is disposed around the outersidewall of the channel layer 201, and the gate dielectric layer 205 isdisposed between the gate layer 204 and the channel layer 201, where thegate dielectric layer 205 is used to separate the gate layer 204 fromthe channel layer 201. In the embodiment, when the gate layer 204 isdisposed around the outer sidewall of the channel layer 201, the gatelayer 204 is disposed surrounding the outer sidewall of the channellayer 201 for a round, and finally the gate layer 204 has a barrelstructure. In this embodiment, the thickness of the gate layer 204 onlyneeds to meet the requirements. Compared with the horizontal width ofthe source layer and the drain layer in the prior art, the wallthickness of the gate layer 204 in this embodiment is much smaller thanthe horizontal width of the source layer and the drain layer in theprior art, so compared with the prior art, the footprint of the formedtransistor is greatly reduced in this embodiment.

Further, on the basis of the above embodiments, this embodiment furtherincludes: an isolation layer 206, which is disposed around the outersurface of the gate layer 204, and is used to isolate adjacenttransistors. That is, in this embodiment, the two transistors areisolated by the isolation layer 206 in order to avoid conduction betweenthe gate layers 204 of two adjacent transistors. In this embodiment, theisolation layer 206 and the gate dielectric layer 205 may be film layersmade of the same material, for example, the isolation layer 206 may alsobe made of silicon oxide. Specifically, in this embodiment, theisolation layer 206 and the gate dielectric layer 205 may be formed by athermal oxidation process. Specifically, the condition of the thermaloxidation process may be 850° C./1 h, and a silicon oxide layer with athickness of 10 nm is formed. The thermal silicon oxide layer on theouter sidewall of the channel layer 201 is used as the gate dielectriclayer 205, and the thermal oxidation layer on the outer side surface ofthe gate layer 204 serves as the isolation layer 206.

Further, on the basis of the above embodiments, this embodiment furtherincludes: a mask layer 207, which covers at least the source layer 202or covers at least the drain layer 203. In this embodiment, as shown inFIG. 2 a , the mask layer 207 covers the source layer 202 and the endsurface of the gate dielectric layer 205 near the source layer 202.During manufacturing the transistor, the mask layer 207 can protect thesource layer 202 in an etching process.

Further, on the basis of the foregoing embodiment, this embodiment alsoincludes a buried oxide layer 208. One of the buried oxide layer 208 andthe mask layer 207 covers at least the source layer 202, and the othercovers at least the drain layer 203. In this embodiment, the mask layer207 covers at least the source layer 202, and the buried oxide layer 208covers at least the drain layer 203. As shown in FIG. 2 a , the buriedoxide layer 208 specifically covers the drain layer 203 and the endsurface of the gate dielectric layer 205 near the drain layer 203. Inthis embodiment, the buried oxide layer 208 is specifically made ofsilicon dioxide, and the buried oxide layer 208 protects the drain layer203.

Further, on the basis of the above embodiments, in this embodiment, inorder to realize the electrical connection of the gate layer 204 withthe word line, the electrical connection of the source layer 202 withthe source line, and the electrical connection of the drain layer 203with the resistance switching device and the bit line, specifically,this embodiment further includes: a first dielectric layer 41, which isdisposed on one end surface of the transistor. In this embodiment, asshown in FIG. 2 a , the first dielectric layer 41 is disposed on an endof the transistor facing the source layer 202. The first dielectriclayer 41 could cover the mask layer 207, and one end surface of the gatelayer 204 and the gate dielectric layer 205, that is, the source layer202 is close to the first dielectric layer 41. Alternatively, in thisembodiment, the first dielectric layer 41 may also be disposed on an endsurface of the transistor near the drain layer 203, and in this way thedrain layer 203 is close to the first dielectric layer 41. In thisembodiment, at least a first metal wire 401 is disposed in the firstdielectric layer 41, and the first metal wire 401 is used toelectrically connect one of the source layer 202 and the drain layer 203near the first dielectric layer 41 to a corresponding wire. For example,in the choice of the source layer 202 and the drain layer 203, if it isthe source layer 202 near the first dielectric layer 41, the first metalwire 401 is used to electrically connect the source layer 202 to thecorresponding source line (SL); in the choice of the source layer 202and the drain layer 203, if it is the drain layer 203 near the firstdielectric layer 41, the first metal wire 401 is used to electricallyconnect the drain layer 203 to the corresponding bit line (BL). Andsince the two ends of the resistance switching device 30 arerespectively connected to the drain layer 203 and the bit line, at thistime, the two ends of the resistance switching device 30 areelectrically connected to the drain layer 203 and the bit line throughthe first metal wire 401, respectively.

Further, on the basis of the above embodiments, this embodiment furtherincludes: a second dielectric layer 42, and the second dielectric layer42 is disposed on one end surface of the transistor facing away from thefirst dielectric layer 41. That is, in this embodiment, the firstdielectric layer 41 and the second dielectric layer 42 are respectivelylocated on two end surfaces of the transistor. As shown in FIG. 2 a ,the first dielectric layer 41 is disposed on one end of the transistornear the source layer 202, and the second dielectric layer 42 isdisposed on the other end of the transistor near the drain layer 203. Orin this embodiment, the first dielectric layer 41 may also be disposedon one end of the transistor near the drain layer 203, and the seconddielectric layer 42 is disposed on the other end of the transistor nearthe source layer 202. In this embodiment, at least a second metal wire402 is disposed in the second dielectric layer 42, and the second metalwire 402 is used to electrically connect one of the source layer 202 andthe drain layer 203 near the second dielectric layer 42 to acorresponding wire. As shown in FIG. 2 a , the second dielectric layer42 is disposed near the drain layer 203, so at this time the secondmetal wire 402 is used to connect to the drain layer 203 to thecorresponding wire. In this embodiment, when the second dielectric layer42 is disposed near the source layer 202, the second metal line is usedto electrically connect the source layer 202 to the corresponding sourceline.

In this embodiment, as shown in FIG. 2 a , when the second dielectriclayer 42 is disposed near the drain layer 203, the resistance switchingdevice 30 may be disposed in the second dielectric layer 42 and near thedrain layer 203. At this time, the resistance switching device 30 isconnected to the drain layer 203 and the bit line through the secondmetal wire 402, respectively. Or in this embodiment, when the firstdielectric layer 41 is disposed near the drain layer 203, the resistanceswitching device 30 may be disposed in the first dielectric layer 41. Atthis time, the resistance switching device 30 is connected to the drainlayer 203 and the bit line through the first metal wire 401,respectively. That is, in this embodiment, the resistance switchingdevice 30 is located in a dielectric layer located near the drain layer203.

In this embodiment, as shown in FIG. 2 a , the resistance switchingdevice 30 includes a lower electrode 33, a resistance switching layer 32and an upper electrode 31 which are sequentially stacked; where thelower electrode 33 is electrically connected to the drain layer, and theupper electrode 31 is electrically connected to the bit line.

In this embodiment, a third metal wire 403 is also provided in the firstdielectric layer 41 or the second dielectric layer 42, that is, thefirst dielectric layer may be provided with the first metal wire 401 andthe third metal wire 403, or the second dielectric layer is providedwith the second metal wire 402 and the third metal wire 403, where thethird metal wire 403 is used to electrically connect the gate layer tothe corresponding word line. As shown in FIG. 2 a , in this embodiment,the third metal wire 403 is specifically disposed in the firstdielectric layer 41, that is, the first dielectric layer 41 is providedwith the first metal wire 401 and the third metal wire 403. In FIG. 2 a, the first metal wire 401 electrically connects the source layer 202 tothe corresponding source line, and the third metal wire 403 electricallyconnects the end of the gate layer 204 facing the first dielectric layer41 to the corresponding word line. Alternatively, in this embodiment,the third metal wire 403 may be located in the second dielectric layer42. At this time, one end of the third metal wire 403 is connected toone end of the gate layer 204 facing the second dielectric layer 42, andthe other end is connected to the word line.

In this embodiment, each of the first metal wire 401, the second metalwire 402, and the third metal wire 403 includes at least one contact andat least one metal layer. The gate layer 204, the source layer 202 andthe drain layer 203 are respectively electrically connected to thecorresponding metal layers through the contact, and the metal layer inthe first dielectric layer 41 is electrically connected to first padsexposed on the first dielectric layer 41, and the metal layer in thesecond dielectric layer 42 is electrically connected to a second padsexposed on the second dielectric layer 42. Specifically, in thisembodiment, as shown in FIG. 2 a , each of the first metal wire 401 andthe third metal wire 403 includes a first contact 61, a second contact62, a first metal layer 51, a second metal layer 52 and a third metallayer 53. The first metal layers 51 in the first metal wire 401 and thethird metal wire 403 are electrically connected to the source layer 202and the gate layer 204 through the first contacts 61, respectively. Thefirst metal layer 51, the second metal layer 52 and the third metallayer 53 are electrically connected to each other through the secondcontacts 62. And the third metal layers 53 in the first metal wire 401and the third metal wire 403 are electrically connected to the firstpads exposed on the first dielectric layer 41. That is, in theembodiment, the gate layer 204 and the source layer 202 are connected tothe first pads 501 through the first metal wire 401 and the third metalwire 403, respectively, and connect to the word line and the powersupply of the source line through the first pads 501. In thisembodiment, the first pads 501 is disposed in the first dielectric layer41 through providing an opening to expose. When the first pads 501 isexposed, it is convenient for the first pads 501 to be electricallyconnected.

It should be noted that the number of contacts and metal layers in thefirst metal wire 401 and the third metal wire 403 includes, but is notlimited to, the first contact 61, the second contact 62, the first metallayer 51, the second metal layer 52 and the third metal layer 53described above. In other embodiments, the number of contacts and metallayers in the source metal wire and the gate metal wire may be one ormore layers, and the specific number of layers is determined accordingto the requirements of circuit wiring.

In this embodiment, as shown in FIG. 2 a , the second metal wire 402specifically includes a third contact 63, a fourth contact 64 and afourth metal layer 54, and the lower electrode 33 and the drain layer203 are electrically connected through the third contact 63, the upperelectrode 31 and the fourth metal layer 54 are electrically connectedthrough the fourth contact 64, and the fourth metal layer 54 iselectrically connected to the second pads 502 exposed on the seconddielectric layer 42.

It should be noted that the number of the contacts and the metal layersin the second metal wire 402 includes, but is not limited to, theabove-mentioned third contact 63, the fourth contact 64, and the fourthmetal layer 54. In other embodiments, the number of contacts and metallayers in the second metal wire 402 may be one or more layers, and thespecific number of layers is determined according to the requirements ofcircuit wiring.

Further, on the basis of the above embodiments, this embodiment furtherincludes: a slide wafer 70, which is disposed on one of the firstdielectric layer 41 and the second dielectric layer 42 far from theburied oxide layer 208. That is, in this embodiment, in the choice ofthe first dielectric layer 41 and the second dielectric layer 42, if thefirst dielectric layer 41 is far from the buried oxide layer 208 (asshown in FIG. 2 a , the second dielectric layer 42 and the buried oxidelayer 208 are located on one side of the transistor, and the firstdielectric layer 41 is located on the other side of the transistor,which means that the first dielectric layer 41 is far from the buriedoxide layer 208), then the slide wafer 70 is disposed on the firstdielectric layer 41, and specifically, the slide wafer 70 is disposed ona side of the first dielectric layer 41 facing away from the transistor.In the choice of the first dielectric layer 41 and the second dielectriclayer 42, if the second dielectric layer 42 is far from the buried oxidelayer 208, then the slide wafer 70 is disposed on the second dielectriclayer 42, and specifically, the slide wafer 70 is disposed on a side ofsecond dielectric layer 42 facing away from the transistor. In thisembodiment, the slide wafer 70 plays a supporting role in themanufacturing process of the drain layer 203 and the resistanceswitching device 30. Specifically, in this embodiment, the slide wafer70 and the first dielectric layer 41 can be fixedly connected bybonding.

Further, on the basis of the above embodiment, in this embodiment, thechannel layer 201 is a columnar structure, which may be specifically acylindrical structure or a square columnar structure, and the gate layer204 is an annular structure disposed around the sidewall of the columnarstructure. In this embodiment, as shown in FIG. 2 a and FIG. 2 b , thechannel layer 201 has a cylindrical structure, and the formed transistoris a vertical cylindrical transistor of which a minimum footprint is4F². It should be noted that, in this embodiment, the channel layer 201may also be a square column, and the gate layer 204 is a square annularstructure at this time.

Second Embodiment

This embodiment provides a transistor as shown in FIG. 2 c . Thetransistor includes a channel layer 201, a gate layer 204 insulated fromthe channel layer 201, and a drain layer 203 and a source layer 202disposed on the channel layer 201. The drain layer 203 and the sourcelayer 202 are vertically distributed on the channel layer 201, that is,the drain layer 203 and the source layer 202 are sequentiallydistributed along the vertical direction of the channel layer 201, forexample, the drain layer 203 may be located above the channel layer 201,the source layer 202 is located below the channel layer 201, and thedrain layer 203 and the source layer 202 are vertically arranged on thechannel layer 201. In this disclosure, since the drain layer 203 and thesource layer 202 are vertically distributed on the channel layer 201,compared with the horizontal distribution of the drain layer and thesource layer in the prior art (as shown in FIG. 1 b ), the footprint ofthe transistor in the horizontal direction is greatly reduced.

In this embodiment, since the drain layer 203 and the source layer 202are vertically distributed on the channel layer 201, carriers migrate ina vertical direction when the transistor is operating. It can beobtained by measuring the transistor provided in this embodiment thatthe columnar transistor has a minimum footprint of 4F² only, and thefootprint of the transistor provided in this embodiment is greatlyreduced compared with the footprint 10F² of the transistor in the priorart. Therefore, when the transistor is applied to a resistive randomaccess memory cell, the area of the resistive random access memory cellis reduced, leading to significant improvement of the memory density.

Further, on the basis of the foregoing embodiment, in this embodiment,the drain layer 203 is disposed on one of the top end and the bottom endof the channel layer 201, and the source layer 202 is disposed on theother. Specifically, as shown in FIG. 2 c , the channel layer 201 has aside surface, a top surface, and a bottom surface. The gate layer 204 isdisposed around the side surface of the channel layer 201 in a round,and finally the gate layer 204 and the channel layer 201 form a columnarstructure together. Meanwhile, the drain layer 203 is disposed on thetop surface of the channel layer 201 and the source layer 202 isdisposed on the bottom surface, that is, the drain layer 203 and thesource layer 202 are located on the upper and lower ends of the channellayer 201, respectively. In this embodiment, for example, the drainlayer 203 may be disposed on the top surface of the channel layer 201and the source layer 202 may be disposed on the bottom surface of thechannel layer 201; or the source layer 202 may also be disposed on thetop surface of the channel layer 201 and the drain layer 203 may bedisposed on the bottom surface of the channel layer 201, to form avertical columnar transistor. Carriers migrate in a vertical directionwhen the transistor is operating.

In the embodiment, the gate layer 204 is disposed around the outersidewall of the channel layer 201, and the gate dielectric layer 205 isdisposed between the gate layer 204 and the channel layer 201, where thegate dielectric layer 205 is used to separate the gate layer 204 fromthe channel layer 201. In the embodiment, when the gate layer 204 isdisposed around the outer sidewall of the channel layer 201, the gatelayer 204 is disposed surrounding the outer sidewall of the channellayer 201 for a round, and finally the gate layer 204 has a barrelstructure. In this embodiment, the thickness of the gate layer 204 onlyneeds to meet the requirements. Compared with the horizontal width ofthe source layer and the drain layer in the prior art, the wallthickness of the gate layer 204 in this embodiment is much smaller thanthe horizontal width of the source layer and the drain layer in theprior art, so compared with the prior art, the footprint of the formedtransistor is greatly reduced in this embodiment.

Further, on the basis of the above embodiments, this embodiment furtherincludes: an isolation layer 206, which is disposed around the outersurface of the gate layer 204, and is used to isolate adjacenttransistors. That is, in this embodiment, the two transistors areisolated by the isolation layer 206 in order to avoid conduction betweenthe gate layers 204 of two adjacent transistors. In this embodiment, theisolation layer 206 and the gate dielectric layer 205 may be film layersmade of the same material, for example, the isolation layer 206 may alsobe made of silicon oxide. Specifically, in this embodiment, theisolation layer 206 and the gate dielectric layer 205 may be formed by athermal oxidation process. Specifically, the condition of the thermaloxidation process may be 850°/1 h, and a silicon oxide layer with athickness of 10 nm is formed. The thermal silicon oxide layer on theouter sidewall of the channel layer 201 is used as the gate dielectriclayer 205, and the thermal oxidation layer on the outer side surface ofthe gate layer 204 serves as the isolation layer 206.

Further, on the basis of the above embodiments, this embodiment furtherincludes: a mask layer 207, which covers at least the source layer 202or covers at least the drain layer 203. In this embodiment, as shown inFIG. 2 a , the mask layer 207 covers the source layer 202 and the endsurface of the gate dielectric layer 205 near the source layer 202.During manufacturing the transistor, the mask layer 207 can protect thesource layer 202 in an etching process.

Further, on the basis of the above embodiments, this embodiment furtherincludes: a buried oxide layer 208. One of the buried oxide layer 208and the mask layer 207 covers at least the source layer 202, and theother covers at least the drain layer 203. In this embodiment, the masklayer 207 covers at least the source layer 202, and the buried oxidelayer 208 covers at least the drain layer 203. As shown in FIG. 2 a ,the buried oxide layer 208 specifically covers the drain layer 203 andthe end surface of the gate dielectric layer 205 near the drain layer203. In this embodiment, the buried oxide layer 208 is specifically madeof silicon dioxide, and the buried oxide layer 208 protects the drainlayer 203.

Further, on the basis of the above embodiment, in order to facilitatethe electrical connection of the source layer 202, the drain layer 203and the gate layer 204 with a corresponding word line, bit line, andsource line, the transistor in this embodiment further includes: a firstdielectric layer 41 and a second dielectric layer 42. At least a firstmetal wire 401 is provided in the first dielectric layer 41, at least asecond metal wire 402 is provided in the second dielectric layer 42, anda third metal wire 403 is also provided in the first dielectric layer 41or the second dielectric layer 42. In this embodiment, for thearrangement of the first dielectric layer 41, the second dielectriclayer 42, the first metal wire 401, the second metal wire 402 and thethird metal wire 403, reference may be made to the first embodiment,which will not be repeated in this embodiment.

Third Embodiment

This embodiment provides a device, which includes a 1T1R resistiverandom access memory according to any of the foregoing embodiments,where the device may be a Microcontroller Unit (Microcontroller Unit,MCU) or may also be other devices containing the above-mentioned 1T1Rresistive random access memory.

Since the device provided in this embodiment includes theabove-mentioned 1T1R resistive random access memory, and the minimumfootprint of the transistor thereof is reduced to 4F², which is greatlyreduced compared with the transistor in the prior art, therefore thearea of each 1T1R resistive random access memory cell is reduced, thememory density is increased and thus the device provided in thisembodiment improves the memory density of the memory cells.

Fourth Embodiment

This embodiment provides a device, which includes a transistor accordingto any of the foregoing embodiments, where the device may be any devicecontaining the above-mentioned transistors.

Since the device provided in this embodiment includes theabove-mentioned transistor, and the minimum footprint of the transistoris reduced to 4F², which is greatly reduced compared with the transistorin the prior art, therefore the area of each transistor is reduced, thetransistor density is increased, and thus the device provided in thisembodiment improves the transistor density of the device.

Fifth Embodiment

FIG. 3 is a schematic flowchart of a manufacturing method for a 1T1Rresistive random access memory according to the fifth embodiment of thepresent disclosure. FIGS. 4 a-4 j are structural schematic diagramsobtained by the steps of the manufacturing method for a 1T1R resistiverandom access memory according to the fifth embodiment of the presentdisclosure.

This embodiment provides a manufacturing method for a 1T1R resistiverandom access memory, which as shown in FIG. 3 includes the followingsteps:

S101: providing a substrate, where the substrate includes a supportlayer, a buried oxide layer 208 and a silicon layer which aresequentially stacked.

In this embodiment, as shown in FIG. 4 a , there are a silicon layer 21,a buried oxide layer 22, and a support layer 23 from top to bottom inthe substrate 20, that is, in this embodiment, the substrate 20 is anSOI wafer, i.e. silicon-on-insulator (SOI). In this embodiment, byadding the buried oxide layer 22 between the silicon layer 21 and thesupport layer 23, on the one hand, a parasitic capacitance can bereduced, and on the other hand, the buried oxide layer 22 plays acalibration role in the subsequent manufacturing of the gate layer 204and facilitates the manufacturing of the drain layer 203. In thisembodiment, the silicon layer 21, the buried oxide layer 22 and thesupport layer 23 may be made of single crystal silicon, silicon dioxide,and single crystal silicon, respectively, and the thicknesses of thesilicon layer 21, the buried oxide layer 22 and the support layer 23 canbe: 1 micrometer, 0.3 micrometer, and 725 micrometers, respectively. Inthis embodiment, when an N-type transistor is manufactured, the siliconlayer 21 is doped with boron (P-type doping), and the dopingconcentration may be 1E15 cm⁻³, and when a P-type transistor ismanufactured, the silicon layer 21 is doped with phosphorus (N-typedoping), and the doping concentration may be 1E15 cm⁻³. It should benoted that the buried oxide layer 22 in the substrate 20 is subsequentlythinned to form the buried oxide layer 208 shown in FIG. 2 a.

S102: forming a mask layer 207 on the silicon layer 21.

In this embodiment, as shown in FIG. 4 b , a mask layer 207 is formed onthe top surface of the silicon layer 21. Specifically, the mask layer207 is formed as a hard mask by depositing silicon dioxide using achemical vapor deposition (Chemical Vapor Deposition, CVD) process, andthe mask layer 207 is formed to facilitate protection of the remainingsilicon layer 21 when an annular groove is formed subsequently byetching. In this embodiment, the thickness of the mask layer 207 isgreater than 180 nm.

S103: forming a single or multiple spaced annular grooves extending fromthe mask layer 207 to the buried oxide layer 22, so that a single ormultiple columnar structures are formed on the substrate 20, and agroove bottom of the annular groove extends into the buried oxide layer22.

In this embodiment, as shown in FIG. 4 b , multiple spaced annulargrooves 2011 are formed extending from the mask layer 207 to the buriedoxide layer 22, and columnar structures are formed in the middle of theannular grooves 2011. Meanwhile, the bottoms of the annular grooves 2011extend into the buried oxide layer 22, so that the columnar structuresinclude the mask layer 207, the silicon layer 21 and the buried oxidelayer 22. In this embodiment, the annular grooves 2011 can bespecifically formed by dry etching. After the etching, the remainingthickness of the mask layer 207 is about 180 nm.

S104: forming a thermal oxide layer on a sidewall of the annular groove2011.

In this embodiment, when the thermal oxidation layer is formed, thespecific condition of the thermal oxidation process is 850° C./1 hour,and the thickness of the formed thermal oxidation layer is 10nanometers. The thermal oxide layer formed on the side surface of thecolumnar structure is used as the gate dielectric layer 205, and thethermal oxide layer formed elsewhere is used as the isolation layer 206to isolate adjacent transistors. Specifically, as shown in FIG. 4 c ,include: forming a first thermal oxide layer (i.e. the gate dielectriclayer 205) on an inner circular sidewall of the annular groove 2011,where the first thermal oxide layer is used to insulate the gate layer204 from the silicon layer 21 of the columnar structure; and forming asecond thermal oxidation layer (i.e. the isolation layer 206) on anouter circular sidewall of the annular groove 2011, where the secondthermal oxidation layer is used to isolate two adjacent gate layers 204.In this embodiment, the thermal oxide layers are specifically made ofsilicon oxide.

S105: forming a gate layer 204 by filling polysilicon in the annulargroove 2011.

In this embodiment, as shown in FIG. 4 d , a low pressure chemical vapordeposition (Low Pressure Chemical Vapor Deposition, LPCVD) process isspecifically used to fill the annular groove 2011 with polysilicon toform a gate layer 204. The gate layer 204 is insulated from the columnarstructure by the gate dielectric layer 205, and the gate layer 204 isisolated from the outer circular sidewall of the annular groove 2011 bythe isolation layer 206. In this embodiment, the formed gate layer 204is a annular gate layer formed around a columnar structure. After theexcess polysilicon is removed by a chemical-mechanical planarization(Chemical-Mechanical Planarization, CMP for short) process, theremaining thickness of the mask layer 207 is about 120 nanometers.

S106: forming a source layer 202 by implanting a P-type doped element oran N-type doped element into an end of the columnar structure facing themask layer 207.

In this embodiment, as shown in FIG. 4 e , a P-type doped element or anN-type doped element may be implanted into the end of the columnarstructure facing the mask layer 207 by ion implantation, so that aheavily doped silicon is formed on the upper surface of the siliconlayer 21, which is used as the source layer 202. In this embodiment,when an N-type transistor is manufactured, phosphorus is doped (N-typedoping), and the doping concentration may be 1E19 cm⁻³. When a P-typetransistor is manufactured, boron is doped (P-type doping), and thedoping concentration may be 1E19 cm⁻³.

S107: forming a drain layer 203 by implanting a P-type doped element oran N-type doped element into an end of the columnar structure where thesilicon layer 21 is in contact with the buried oxide layer 22.

In this embodiment, the source layer 202, the gate layer 204 and thegate dielectric layer 205 of the transistor are formed through steps101-106. In order to form a drain layer 203 on the back side of thesubstrate 20, at this time, the substrate 20 is turned over (as shown inFIG. 4 g ), the support layer 23 faces upward, the silicon layer 21faces downward, and the drain layer 203 is formed on the back side ofthe SOI wafer. The silicon layer 21 between the drain layer 203 and thesource layer 202 is a channel layer 201. In this way, a transistor isformed through steps 101-107. In this embodiment, phosphorus (N-typetransistor) or boron (P-type transistor) is specifically implanted intoan end of the columnar structure near the buried oxide layer 22 by anion implantation method to form the drain layer 203. The dopingconcentration may specifically be 1E19 cm⁻³. The doped region isannealed with a laser annealing process to activate and repair latticedamage. Due to the characteristics of instantaneous high temperature,the laser annealing can allow heat to be concentrated in the surfaceregion, so as not to damage the metal below the surface.

S108: disposing a resistance switching device 30 near the drain layer203, where one end of the resistance switching device 30 is electricallyconnected to the drain layer 203.

In this embodiment, after the transistor is formed, start to manufacturethe resistance switching device and the metal wires. Specifically, theresistance switching device 30 is disposed near the drain layer 203.Since the source layer 202 is located on the front side of the substrate20 and the drain layer 203 is located on the back side of the substrate20. Therefore, in this embodiment, the resistance change device 30 isdisposed on the back side of the substrate 20, that is, the resistanceswitching device is manufactured on the back side of the SOI substratein this embodiment. Meanwhile, in this embodiment, one end of theresistance switching device 30 is electrically connected to the drainlayer 203, and a 1T1R resistive random access memory is finallymanufactured.

In this embodiment, a drain layer 203 and a source layer 202 arerespectively disposed on the front and back sides of a substrate 20including a silicon layer 21, a buried oxide layer 22 and a supportlayer 23, that is, a vertical columnar transistor is made based on anSOI substrate 20. Compared with the prior art, the manufacturing processis simplified. Meanwhile, the RRAM process needs to be completed in aspecial processing plant, because the manufacturing of the resistanceswitching device 30 involves some special materials, such as Au, Ag, Pt,etc. used as the material of electrode and Pr_(0.7)Ca_(0.3)MnO₃ (PCMO)used as the material of the resistance switching layer 32, that areincompatible with the traditional CMOS (Complementary Metal OxideSemiconductor) process. In this disclosure, the resistance switchingdevice 30 can be made on the back side of the SOI wafer (i.e. thesubstrate 20), so that the transistor process and the RRAM process canbe carried out in stages (the process of making resistance switchingdevice and subsequent metal wire is collectively called RRAM), whichprovides more possibilities for the option of the material of theresistance switching device 30. Meanwhile, the minimum footprint of thetransistor in the 1T1R resistive random access memory manufactured bythis disclosure is only 4F² and compared with the transistor in theprior art, the footprint of the transistor is greatly reduced, whichleads to a great reduction in the area of each 1T1R resistive randomaccess memory cell and an increase in the memory density. Therefore, themanufacturing method for the 1T1R resistive random access memoryprovided in this embodiment simplifies the manufacturing process of the1T1R resistive random access memory, provides more possibilities for theoption of the material of the resistance switching device 30, andreduces the footprint of the transistor and increases the memorydensity, thereby solving the problem of the existing 1T1R resistiverandom access memory that the memory density is limited due to that thearea of transistor cannot be reduced.

Further, on the basis of the above embodiments, in this embodiment,before step 106, the method further includes: reducing the thickness ofthe masking layer 207 to 8 nm to 20 nm. That is, in this embodiment,before implanting a P-type doped element or an N-type doped element intothe columnar structure to form the source layer 202, the thickness ofthe mask layer 207 needs to be reduced, which is convenient for theP-type doped element or the N-type doped element to be implanted intothe silicon layer 21. In this embodiment, as shown in FIG. 4 e , thethickness of the mask layer 207 is reduced to about 10 nm.

Further, on the basis of the above embodiments, before step 107, thatis, before implanting a P-type doped element or an N-type doped elementinto the silicon layer 21 of the columnar structure near the buriedoxide layer 22 to form the drain layer 203, as shown in FIG. 4 g , thisembodiment further includes: removing the support layer 23 and reducingthe thickness of the buried oxide layer 22 to 8 nm to 20 nm, to form theburied oxide layer 208 in FIG. 2 a . Specifically, it is divided intothree stages: the first stage is to use mechanical thinning to reducethe thickness of the support layer 23 from 725 micrometers to about 20micrometers, where a standard mechanical thinning process includes roughgrinding, fine grinding, polishing, etc.; the second stage is to use dryetching to remove the remaining silicon of the support layer 23completely, where the etching is stopped after reaching the buried oxidelayer 22, and the dry etching uses a recipe with a selection ratio of10:1 or more; the third stage is to use wet etching to remove a certainthickness of the buried oxide layer 22. The final thickness of theremaining buried oxide layer 22 is about 10 nanometers and the structureof that is shown in FIG. 4 g . After the buried oxide layer 22 isthinned, a P-type doped element or an N-type doped element is implantedby ion implantation to form the drain layer 203.

Further, on the basis of the above embodiment, in order to facilitatethe electrical connection of the gate layer 204 and the source layer 202with the source line, the word line, and other circuits, specifically,after step 106, a front metal interconnection wire needs to be produced.Specifically, the method also includes: forming a lower dielectric layer411 on the mask layer 207 and on an end surface of the gate layer 204near the mask layer 207, as shown in FIG. 4 f , forming a gate metallayer, a source metal layer, and first pads 501 that is electricallyconnected to the gate metal layer and the source metal layer on thelower dielectric layer 411, covering a first inter-metal dielectriclayer 412 on the lower dielectric layer 411 on which the gate metallayer, the source metal layer and the first pads are formed, where thegate metal layer and the source metal layer are electrically connectedto the gate layer and the source layer through contacts (e.g. the firstcontact 61 and the second contact 62) respectively, and disposing aslide wafer 70 on the first inter-metal dielectric layer 412 (as shownin FIG. 4 g ), where the first inter-metallic dielectric layer 412 andthe slide wafer 70 are fixed together by a bonding method, and the slidewafer 70 plays a supporting role in the subsequent thinning process ofremoving the support layer 23 and the buried oxide layer 22. In thisembodiment, the lower dielectric layer 411 and the first inter-metallicdielectric layer 412 form the aforementioned first dielectric layer 41together. In this embodiment, the gate metal layer and the source metallayer each include: a first metal layer 51, a second metal layer 52 anda third metal layer 53. That is, the gate metal layer is composed of afirst metal layer 51, a second metal layer 52 and a third metal layer53, and the source metal layer is also composed of a first metal layer51, a second metal layer 52 and a third metal layer 53.

In this embodiment, it should be noted that the lower dielectric layer411 may be only provided with the source metal layer and the first pads501 that is electrically connected to the source metal layer. That is,in this embodiment, the metal layer for electrically connecting with thegate layer 204 is not provided in the first dielectric layer 41, and thegate metal layer may be provided on the upper dielectric layer 421, thatis, the gate metal layer is provided in the second dielectric layer 42.

It should be noted that during manufacturing the first metal layer 51,the second metal layer 52 and the third metal layer 53, each metal layerneeds to be covered with a first inter-metal dielectric layer 412, andthen another metal layer is then disposed on the first inter-metaldielectric layer 412 until all the metal layers are disposed. In thisembodiment, there are three metal layer (i.e. the first metal layer 51,the second metal layer 52, and the third metal layer 53) in the firstdielectric layer 41. In other embodiments, the first dielectric layer 41may have one or more metal layers, and the specific number of layers isdetermined according to the requirements of circuit wiring.

In this embodiment, the first pads 501 and the third metal layer 53 areelectrically connected, where the first pads 501 will subsequently beperform with a pad open process, so that the first pads 501 can beelectrically connected to an external circuit board.

Further, on the basis of the above embodiment, in this embodiment, inorder to electrically connect the drain layer 203 with the resistanceswitching device 30 and the bit line, therefore, after the above step107, as shown in FIG. 4 i , the method further includes: forming anupper dielectric layer 421 on the buried oxide layer 22 and on an endsurface of the gate layer 204 near the buried oxide layer 22, andcorrespondingly, the disposing a resistance switching device 30 near thedrain layer 203 specifically includes: disposing the resistanceswitching device 30 on the upper dielectric layer 421 at a positioncorresponding to the drain layer 203, where the resistance switchingdevice 30 includes a lower electrode 33, a resistance switching layer 32and an upper electrode 31 that are stacked, and the lower electrode 33is electrically connected to the drain layer 203 through a third contact63.

In this embodiment, after disposing the resistance switching device 30,the method further includes:

disposing a second inter-metal dielectric layer 422 on the upperdielectric layer 421 on which the resistance switching device 30 isformed; forming a drain metal layer (i.e. the fourth metal layer 54) anda second pads 502 that is electrically connected to the drain metallayer on the second inter-metal dielectric layer 422, where the drainmetal layer is electrically connected to the upper electrode 31 throughthe fourth contact 64; covering a third inter-metal dielectric layer 423on the second inter-metal dielectric layer 422 on which the drain metallayer and the second pads are formed. In this embodiment, the secondinter-metal dielectric layer 422 and the third inter-metal dielectriclayer 423 constitute the above-mentioned second dielectric layer 42,where the number of layers of the second inter-metallic dielectric layer422 and the third inter-metallic dielectric layer 423 is specificallyrelated to the metal layer disposed in the second dielectric layer 42,and the second inter-metal dielectric layer 422 and the thirdinter-metal dielectric layer 423 are only used to distinguish theinter-metal dielectric layers. In this embodiment, the upper dielectriclayer 421, the second inter-metal dielectric layer 422 and the thirdinter-metal dielectric layer 423 form the above-mentioned seconddielectric layer 42, where the upper dielectric layer 421, the secondinter-metal dielectric layer 422 and the third inter-metal dielectriclayer 423 are all insulating layers that are insulated from the metallayer. In this embodiment, the second pads 502 will be subsequentlyperformed with a pad open process, so that the second pads 502 can beelectrically connected to an external circuit board.

In this embodiment, after covering the third inter-metal dielectriclayer 423 on the second inter-metal dielectric layer 422 on which thedrain metal layer and the second pads 502 are formed, as shown in FIG. 4j , the method further includes: opening a first opening 5011 and asecond opening 5021 on the third inter-metal dielectric layer 423 atpositions corresponding to the first pads 501 and the second pads 502,respectively, where the first opening 5011 extends to the surface of thefirst pads 501, and the second opening 5021 extends to the surface ofthe second pads 502. That is, a pad open process is performed, so thatthe transistor and the resistance switching device 30 are electricallyconnected to other circuits on the circuit board through the first pads501 and the second pads 502.

In the description of the present disclosure, it should be noted thatthe terms “dispose”, “connect with”, and “connect to” should beunderstood in a broad sense unless otherwise specified and limited. Forexample, a connection may be a fixed connection, or may be an indirectconnection through an intermediate medium, or may also be an internalconnection of two components or an interaction between two components.For those skilled in the art, the specific meanings of the above termsin the present disclosure can be understood according to specificsituations.

In the description of the present disclosure, it should be understoodthat the orientational or positional relationship indicated by the terms“up”, “down”, “front”, “back”, “vertical”, “horizontal”, “top”,“bottom”, “inside”, “outside” and the like are based on theorientational or positional relationship shown in the drawings, and areonly for the convenience of describing the present disclosure andsimplifying description, but not to indicate or imply that a device orcomponent referred to must have a specific orientation, or beconstructed and operated in a specific orientation, and therefore shouldnot be understood as a limitation to the present disclosure. In thedescription of the present disclosure, “multiple” means two or more,unless it is specifically and precisely specified otherwise.

The terms “first”, “second”, “third”, “fourth”, etc. (if any) in thedescription and claims of the present disclosure and the above-mentioneddrawings are used to distinguish similar objects, and need not be usedfor describing a particular order or sequence. It should be understoodthat the data used in this way are interchangeable where appropriate, sothat the embodiments of the present disclosure described herein can beimplemented in an order other than those illustrated or describedherein, for example. Furthermore, the terms “include” and “have” and anyof their variations are intended to cover non-exclusive inclusions, forexample, a process, method, system, product, or device that includes aseries of steps or units need not be limited to those explicitly listedsteps or units, but may instead include other steps or units notexplicitly listed or inherent to these processes, methods, products orequipment.

Finally, it should be stated that: the above embodiments are only usedto illustrate the technical solution of the present disclosure, but notto limit. Although the present disclosure has been described in detailwith reference to the foregoing embodiments, those skilled in the artwill understand: they can still modify the technical solutions describedin the foregoing embodiments, or replace some or all of the technicalfeatures equivalently, and these modifications or replacements do notdeviate the essence of the corresponding technical solutions from thescope of the technical solutions of the embodiments of the presentdisclosure.

What is claimed is:
 1. A 1T1R resistive random access memory,comprising: a memory cell array composed of multiple 1T1R resistiverandom access memory cells, each 1T1R resistive random access memorycell comprising a transistor and a resistance switching device (30);wherein the transistor comprises a channel layer (201), a gate layer(204) insulated from the channel layer (201), and a drain layer (203)and a source layer (202) that are disposed on the channel layer (201),wherein the drain layer (203) and the source layer (202) are verticallydistributed on the channel layer (201); the resistance switching device(30) is disposed near the drain layer (203), and two ends of theresistance switching device (30) are used to connect to the drain layer(203) and a bit line, respectively, and the gate layer (204) is used toelectrically connect to a word line, and the source layer (202) is usedto connect to a source line; the transistor further comprising: a masklayer (207), wherein the mask layer (207) covers at least the sourcelayer (202) or covers at least the drain layer (203).
 2. The 1T1Rresistive random access memory according to claim 1, further comprising:an isolation layer (206), wherein the isolation layer (206) is disposedaround an outer surface of the gate layer (204) and is used to isolateadjacent transistors.
 3. The 1T1R resistive random access memoryaccording to claim 1, further comprising: a buried oxide layer (208),wherein one of the buried oxide layer (208) and the mask layer (207)covers at least the source layer (202), and the other covers at leastthe drain layer (203).
 4. The 1T1R resistive random access memoryaccording to claim 3, further comprising: a first dielectric layer (41),wherein the first dielectric layer (41) is provided on one end surfaceof the transistor, and at least a first metal wire (401) is provided inthe first dielectric layer (41), and the first metal wire (401) is usedto electrically connect one of the source layer (202) and the drainlayer (203) near the first dielectric layer (41) to a correspondingwire; a second dielectric layer (42), wherein the second dielectriclayer (42) is disposed on one end surface of the transistor facing awayfrom the first dielectric layer, and at least a second metal wire (402)is provided in the second dielectric layer (42), wherein the secondmetal wire (402) is used to electrically connect one of the source layer(202) and the drain layer (203) near the second dielectric layer (42) toa corresponding wire; a slide wafer (70), wherein the slide wafer (70)is disposed on one of the first dielectric layer (41) and the seconddielectric layer (42) far from the buried oxide layer (208).
 5. The 1T1Rresistive random access memory according to claim 1, wherein theresistance switching device (30) comprises a lower electrode (33), aresistance switching layer (32) and an upper electrode (31) which aresequentially stacked, and wherein the lower electrode (33) iselectrically connected to the drain layer (203), and the upper electrode(31) is electrically connected to the bit line.
 6. The 1T1R resistiverandom access memory according to claim 3, further comprising: a firstdielectric layer (41), wherein the first dielectric layer (41) isprovided on one end surface of the transistor, and at least a firstmetal wire (401) is provided in the first dielectric layer (41), and thefirst metal wire (401) is used to electrically connect one of the sourcelayer (202) and the drain layer (203) near the first dielectric layer(41) to a corresponding wire; a second dielectric layer (42), whereinthe second dielectric layer (42) is disposed on one end surface of thetransistor facing away from the first dielectric layer, and at least asecond metal wire (402) is provided in the second dielectric layer (42),wherein the second metal wire (402) is used to electrically connect oneof the source layer (202) and the drain layer (203) near the seconddielectric layer (42) to a corresponding wire; wherein a third metalwire (403) is further disposed in the first dielectric layer (41) or thesecond dielectric layer (42), wherein the third metal wire (403) is usedto electrically connect the gate layer (204) to a corresponding wordline; wherein each of the first metal wire (401), the second metal wire(402) and the third metal wire (403) comprises at least one contact andat least one metal layer, the gate layer (204), the source layer (202)and the drain layer (203) are respectively electrically connected to acorresponding metal layer through the contact, the metal layer in thefirst dielectric layer (41) is electrically connected to first pads(501) exposed on the first dielectric layer (41), and the metal layer inthe second dielectric layer (42) is electrically connected to a secondpads (502) exposed on the second dielectric layer (42).
 7. The 1T1Rresistive random access memory according to claim 1, wherein the channellayer (201) is a columnar structure, and the gate layer (204) is a anannular structure disposed around a sidewall of the columnar structure.8. The 1T1R resistive random access memory according to claim 3, whereinthe mask layer, the buried oxide layer and the isolation layer are allmade of silicon oxide.
 9. A transistor, comprising a channel layer(201), a gate layer (204) insulated from the channel layer, and a drainlayer (203) and a source layer (202) disposed on the channel layer(201), wherein the drain layer (203) and the source layer (202) arevertically distributed on the channel layer (201); wherein thetransistor further comprises: a mask layer (207), wherein the mask layer(207) covers at least the source layer (202) and an end surface of agate dielectric layer (205) near the source layer (202), the gatedielectric layer (205) disposed between the gate layer (204) and thechannel layer (201), and the gate dielectric layer (205) and the sourcelayer (202) disposed on the same side of the mask layer (207).
 10. Thetransistor according to claim 9, further comprising: an isolation layer(206), wherein the isolation layer (206) is disposed around an outersurface of the gate layer (204) and is used to isolate adjacenttransistors.
 11. The transistor according to claim 9, furthercomprising: a buried oxide layer (208), wherein the buried oxide layer(208) covers at least the drain layer (203).
 12. A method formanufacturing a 1T1R resistive random access memory according to claim1, wherein the method comprises: providing a substrate which comprises asupport layer, a buried oxide layer and a silicon layer which aresequentially stacked; forming a mask layer on the silicon layer; forminga single or multiple spaced annular grooves extending from the masklayer to the buried oxide layer, so that a single or multiple columnarstructures are formed on the substrate, and a groove bottom of theannular groove extends into the buried oxide layer; forming a thermaloxide layer on a sidewall of the annular groove; forming a gate layer byfilling polysilicon in the annular groove; forming a source layer byimplanting a P-type doped element or an N-type doped element into an endof the columnar structure facing the mask layer; forming a drain layerby implanting a P-type doped element or an N-type doped element into anend of the columnar structure where the silicon layer is in contact withthe buried oxide layer; disposing a resistance switching device near thedrain layer, wherein one end of the resistance switching device iselectrically connected to the drain layer.
 13. The manufacturing methodaccording to claim 12, before the implanting a P-type doped element oran N-type doped element into an end of the columnar structure facing themask layer, further comprising: reducing a thickness of the maskinglayer to 8 nm to 20 nm.
 14. The manufacturing method according to claim12, wherein the forming a thermal oxide layer on a sidewall of theannular groove comprises: forming a first thermal oxide layer on aninner circular sidewall of the annular groove, wherein the first thermaloxide layer is used to insulate the gate layer from the silicon layer ofthe columnar structure; forming a second thermal oxidation layer on anouter circular sidewall of the annular groove, wherein the secondthermal oxidation layer is used to isolate two adjacent gate layers. 15.The manufacturing method according to claim 12, before the implanting aP-type doped element or N-type doped element into an end of the columnarstructure where the silicon layer is in contact with the buried oxidelayer, further comprising: removing the support layer; reducing athickness of the buried oxide layer to 8 nm to 20 nm.
 16. Themanufacturing method according to claim 12, after the implanting aP-type doped element or an N-type doped element into an end of thecolumnar structure facing the mask layer, further comprising: forming alower dielectric layer on the mask layer and on an end surface of thegate layer near the mask layer; forming a gate metal layer, a sourcemetal layer and first pads that is electrically connected to the gatemetal layer and the source metal layer, on the lower dielectric layer;covering a first inter-metal dielectric layer on the lower dielectriclayer on which the gate metal layer, the source metal layer and thefirst pads are formed, wherein the gate metal layer and the source metallayer are electrically connected to the gate layer and the source layerthrough a contact, respectively; disposing a slide wafer on the firstinter-metal dielectric layer.
 17. The manufacturing method according toclaim 16, after the implanting a P-type doped element or N-type dopedelement into an end of the columnar structure where the silicon layer isin contact with the buried oxide layer, further comprising: forming anupper dielectric layer on the buried oxide layer and on an end surfaceof the gate layer near the buried oxide layer; the disposing aresistance switching device near the drain layer includes: disposing theresistance switching device on the upper dielectric layer at a positioncorresponding to the drain layer, wherein the resistance switchingdevice comprises a lower electrode, a resistance switching layer and anupper electrode that are stacked, and the lower electrode iselectrically connected to the drain layer through a contact.
 18. Themanufacturing method according to claim 17, after the disposing theresistance switching device on the upper dielectric layer at a positioncorresponding to the drain layer, further comprising: disposing a secondinter-metal dielectric layer on the upper dielectric layer on which theresistive random device is formed; forming a drain metal layer and asecond pads that is electrically connected to the drain metal layer, onthe second inter-metal dielectric layer, wherein the drain metal layeris electrically connected to the upper electrode through a contact;covering a third inter-metal dielectric layer on the second inter-metaldielectric layer on which the drain metal layer and the second pads areformed.
 19. The manufacturing method according to claim 18, after thecovering a third inter-metal dielectric layer on the second inter-metaldielectric layer on which the drain metal layer and the second pads areformed, further comprising: opening a first opening and a second openingon the third inter-metal dielectric layer at positions corresponding tothe first pads and the second pads, respectively, wherein the firstopening extends to a surface of the first pads, and the second openingextends to a surface of the second pads.